This invention relates to electronic circuit design tools and methodology (expressed as software) that are typically used to capture the design intent and the specific circuit behavior during the design of a circuit. These tools are also used to communicate the design intent and the circuit behavior between a circuit designer and other technical personnel such as design team member. To make the process easier, textual and graphical tools are embedded in these circuit design tools so as to enhance the understanding and visualization of various aspects of the circuit design. These textual and graphical tools provide an interface in order to display waveforms of various signals and in order to highlight various characteristics that are associated with the circuit design. To display waveforms these tools make use of various kinds of timing waveform diagrams, finite state machine transition diagrams, process flowcharts, etc. Indeed, such graphical representations are standard methods that are currently being used in the circuit design industry. Computer Aided Design (CAD) environments combine the design tools with the graphical tools for this purpose. CAD tools typically provide software-automated environments in order to enable communication between a designer and various kinds of computer-related tools, and by doing so, the designer is able to capture, analyze, and manipulate the design data more effectively and efficiently.
Recently, effort has been directed towards improving the visualization of the circuits and the various parameters guiding the circuit design. This involves display of various waveforms and expressions corresponding to the characteristic of a circuit design. Existing waveform viewers have the ability to display the waveform of the signals and also display corresponding expressions in separate windows. However, the user still has to sift through and understand the plethora of information provided by the waveform. In order to simplify the manual analysis of the waveform, U.S. patent application Ser. No. 10/401,315 filed on Mar. 27, 2003, referenced above, describes a system and process that facilitates this analysis/debugging activity by providing the ability to find out why a signal has a specific value by cross referencing to the source code (the “Why” function). The present invention looks at this analysis/debugging activity from a complementary angle.
Apart from the need to find out “why” a signal has a certain value, there is also a need for information illustrating how signals, which contribute to the violation (or satisfaction) of a property, are affected by a selected signal, e.g., a signal chosen by the user at a specific time step of the waveform. That is, it is important to see how the value of a selected signal at a specific time step affects the surrounding logic with respect to determining the validity of the property. This information is more useful compared to a feature that just shows all signals driven by a selected signal, e.g., the register transfer language (RTL) load. It will aid the user in understanding how the property fails.
In addition, the information presented to the user should be relevant. The selected signal should be directly responsible for the value of the set of surrounding signals which contribute to the validity of the property. In this context, directly responsible means that the selected signal relevantly determines the value of the surrounding signal either in complete conjunction with other inputs (for example, an AND gate where all inputs, including the selected input, are 1) or regardless of other inputs (for example, an AND gate where the selected input is 0).
A variation of the above problem is finding out how the specific value of a selected signal at a specific time step affects surrounding logic, without regard to a property. The user should be able to select a signal, and find all the other signals in which the selected signal at a specific time step is directly responsible for its value. This information is useful to general understanding of the design.
What is needed is a system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon the value of the selected signal, where the set of signals to be examined is limited to (1) RTL load signals, (2) analysis region signals and/or (3) signals affecting the proof target.